Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control (Q2986000)
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scientific article; zbMATH DE number 6714107
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| English | Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control |
scientific article; zbMATH DE number 6714107 |
Statements
Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control (English)
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11 May 2017
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chaotic system
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fixed-point algorithm
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state machine control
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verilog HDL
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FPGA implementation
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0.8686393
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0.8500562
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0.8465656
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