Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control
DOI10.1142/S0218127417500407zbMath1360.65030OpenAlexW2606334304MaRDI QIDQ2986000
Zhuosheng Lin, Jinhu Lü, Simin Yu, Jianbin He, Yuqiong Wen, Mo Qiu
Publication date: 11 May 2017
Published in: International Journal of Bifurcation and Chaos (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1142/s0218127417500407
Cryptography (94A60) Data encryption (aspects in computer science) (68P25) Random number generation in numerical analysis (65C10) Strange attractors, chaotic dynamics of systems with hyperbolic behavior (37D45)
Related Items (1)
Cites Work
This page was built for publication: Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control