Mapping Interleaving Laws to Parallel Turbo and LDPC Decoder Architectures (Q3547697)
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| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Mapping Interleaving Laws to Parallel Turbo and LDPC Decoder Architectures |
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Statements
Mapping Interleaving Laws to Parallel Turbo and LDPC Decoder Architectures (English)
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21 December 2008
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Low-density parity-check, codes (LDPC)
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memory mapping
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parallel implementation
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turbo codes
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