Mapping Interleaving Laws to Parallel Turbo and LDPC Decoder Architectures

DOI10.1109/TIT.2004.833353MaRDI QIDQ3547697zbMATHFDO

Authors Alberto Tarable, Sergio Benedetto, Guido Montorsi

Publication date 21 December 2008

Published in IEEE Transactions on Information Theory (Search for Journal in Brave)

zbMATH Keywords

parallel implementationturbo codesmemory mappingLow-density parity-check, codes (LDPC)

Mathematics Subject Classification ID

Decoding (94B35) Combined modulation schemes (including trellis codes) in coding theory (94B12)

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• Parallel access by butterfly networks for any degree permutation polynomial and ARP interleavers

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