Mapping Interleaving Laws to Parallel Turbo and LDPC Decoder Architectures

DOI10.1109/TIT.2004.833353zbMATH Open1298.94144MaRDI QIDQ3547697FDOQ3547697

Authors: Alberto Tarable, Sergio Benedetto, Guido Montorsi 

Publication date: 21 December 2008

Published in: IEEE Transactions on Information Theory (Search for Journal in Brave)

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zbMATH Keywords

parallel implementationturbo codesmemory mappingLow-density parity-check, codes (LDPC)

Mathematics Subject Classification ID

Decoding (94B35) Combined modulation schemes (including trellis codes) in coding theory (94B12)

Cited In (2)

• Parallel access by butterfly networks for any degree permutation polynomial and ARP interleavers
• Memory-reduced maximum a posteriori probability decoding for high-throughput parallel turbo decoders

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