On nominal delay minimization in LUT-based FPGA technology mapping (Q4331997)
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scientific article; zbMATH DE number 983679
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| English | On nominal delay minimization in LUT-based FPGA technology mapping |
scientific article; zbMATH DE number 983679 |
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On nominal delay minimization in LUT-based FPGA technology mapping (English)
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27 February 1997
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Combinational logic synthesis
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FPGA
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Technology mapping
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0.8733981847763062
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0.865522563457489
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0.7230672836303711
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