On nominal delay minimization in LUT-based FPGA technology mapping

DOI10.1016/0167-9260(94)90012-4zbMATH Open0875.68152OpenAlexW2023455730MaRDI QIDQ4331997FDOQ4331997

Jason Cong, Yuzheng Ding

Publication date: 27 February 1997

Published in: Integration (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0167-9260(94)90012-4

zbMATH Keywords

FPGACombinational logic synthesisTechnology mapping

Mathematics Subject Classification ID

Complexity classes (hierarchies, relations among complexity classes, etc.) (68Q15) Parallel algorithms in computer science (68W10) Computer system organization (68M99)

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