On nominal delay minimization in LUT-based FPGA technology mapping

DOI10.1016/0167-9260(94)90012-4MaRDI QIDQ4331997zbMATH OpenOpenAlexFDO

Authors Jason Cong, Yuzheng Ding

Publication date 27 February 1997

Published in Integration (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0167-9260(94)90012-4

zbMATH Keywords

FPGACombinational logic synthesisTechnology mapping

Mathematics Subject Classification ID

Complexity classes (hierarchies, relations among complexity classes, etc.) (68Q15) Parallel algorithms in computer science (68W10) Computer system organization (68M99)

Recommendations

• Technology mapping and placement for delay-minimization in LUT-based FPGA design
• Simultaneous area and delay minimum K-LUT mapping for K-exact networks
• scientific article; zbMATH DE number 811541
• Technology mapping for area and speed
• scientific article; zbMATH DE number 1844658

Cited in

(1)

• scientific article; zbMATH DE number 1844658 (Why is no real title available?)

This page was built for publication: On nominal delay minimization in LUT-based FPGA technology mapping

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4331997)