Technology mapping for area and speed

DOI10.1016/S0167-9260(99)00023-1MaRDI QIDQ4955656zbMATH OpenOpenAlexFDO

Authors D. Jongeneel, Ralph H. J. M. Otten

Publication date 4 June 2000

Published in Integration (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/s0167-9260(99)00023-1

zbMATH Keywords

acyclic networkspeed optimization

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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(2)

• On nominal delay minimization in LUT-based FPGA technology mapping
• Simultaneous area and delay minimum K-LUT mapping for K-exact networks

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