Technology mapping for low power in logic synthesis

DOI10.1016/0167-9260(96)00002-8zbMATH Open0875.94131OpenAlexW2037703867MaRDI QIDQ4332017FDOQ4332017

Authors: Vivek Kumar Tiwari, Pranav Ashar, Sharad Malik 

Publication date: 27 February 1997

Published in: Integration (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0167-9260(96)00002-8

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Mathematics Subject Classification ID

Analytic circuit theory (94C05)

Cited In (6)

• Technology mapping of multi-output functions leading to the reduction of dynamic power consumption in FPGAs
• The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications
• Computation of signal output probability for Boolean functions represented by OBDD
• Logic synthesis method for power dissipation reduction in combinational digital circuits
• Cell selection from technology libraries for minimizing power
• GATE RESIZING TO REDUCE POWER CONSUMPTION

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