Pranav Ashar

Available identifiers

zbMath Open ashar.pranavMaRDI QIDQ685102

List of research outcomes

Publication	Date of Publication	Type
Correct Hardware Design and Verification Methods	2010-02-05	Paper
Efficient SAT-based bounded model checking for software verification	2008-10-07	Paper
Tools and Algorithms for the Construction and Analysis of Systems	2005-11-10	Paper
Computer Aided Verification	2005-08-25	Paper
Technology mapping for low power in logic synthesis	1997-02-27	Paper
Path-delay-fault testability properties of multiplexor-based networks	1993-12-20	Paper
Gate-delay-fault testability properties of multiplexor-based networks	1993-09-30	Paper

Research outcomes over time

This page was built for person: Pranav Ashar