Gate-delay-fault testability properties of multiplexor-based networks

DOI10.1007/BF01383945MaRDI QIDQ685105zbMATH OpenFDO

Authors Pranav Ashar, Srinivas Devadas, Kurt Keutzer

Publication date 30 September 1993

Published in Formal Methods in System Design (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/BF01383945

zbMATH Keywords

Binary Decision Diagramgate-delay faultslogic circuitsstuck-at faultssynthesis for test

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

Recommendations

• Synthesis of delay fault testability circuits
• Synthesis for testability: Binary Decision Diagrams
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• Path delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method
• Path delay fault test design for circuits obtained by covering ROBDDs with CLBs

Cites work

• Binary Decision Diagrams
• Graph-Based Algorithms for Boolean Function Manipulation
• scientific article; zbMATH DE number 3590198 (Why is no real title available?)

Cited in

(1)

• Synthesis of delay fault testability circuits

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