Simultaneous area and delay minimum K-LUT mapping for K-exact networks

DOI10.1016/0167-9260(96)00004-1zbMATH Open0875.68435OpenAlexW2023417467MaRDI QIDQ4332020FDOQ4332020

Shashidhar Thakur, D. F. Wong

Publication date: 27 February 1997

Published in: Integration (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0167-9260(96)00004-1

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Mathematics Subject Classification ID

Complexity classes (hierarchies, relations among complexity classes, etc.) (68Q15)

Cited In (1)

• On nominal delay minimization in LUT-based FPGA technology mapping

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