A pipelined-loop-compatible architecture and algorithm to reduce variable-length sets of floating-point data on a reconfigurable computer (Q436815)
From MaRDI portal
!
This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use the normal view instead:
scientific article; zbMATH DE number 6059793
| Language | Label | Description | Also known as |
|---|---|---|---|
| default for all languages | No label defined |
||
| English | A pipelined-loop-compatible architecture and algorithm to reduce variable-length sets of floating-point data on a reconfigurable computer |
scientific article; zbMATH DE number 6059793 |
Statements
A pipelined-loop-compatible architecture and algorithm to reduce variable-length sets of floating-point data on a reconfigurable computer (English)
0 references
26 July 2012
0 references
FPGA
0 references
pipeline
0 references
reduction
0 references
accumulator
0 references
sparse matrix
0 references
iterative solver
0 references
reconfigurable computer
0 references
0.7158005833625793
0 references
0.7129150032997131
0 references
0.7091516852378845
0 references
0.7074928879737854
0 references
