A pipelined-loop-compatible architecture and algorithm to reduce variable-length sets of floating-point data on a reconfigurable computer

DOI10.1016/J.JPDC.2008.03.004MaRDI QIDQ436815zbMATH OpenOpenAlexFDO

Authors Gerald R. Morris, Viktor K. Prasanna

Publication date 26 July 2012

Published in Journal of Parallel and Distributed Computing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/j.jpdc.2008.03.004

zbMATH Keywords

sparse matrixiterative solverreductionFPGApipelineaccumulatorreconfigurable computer

Mathematics Subject Classification ID

Theory of compilers and interpreters (68N20) Computer system organization (68M99)

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Cites work

• scientific article; zbMATH DE number 53772 (Why is no real title available?)
• scientific article; zbMATH DE number 733664 (Why is no real title available?)
• scientific article; zbMATH DE number 1953444 (Why is no real title available?)
• Methods of conjugate gradients for solving linear systems

Cited in

(5)

• Improving software performance with configurable logic
• scientific article; zbMATH DE number 1941118 (Why is no real title available?)
• scientific article; zbMATH DE number 1941119 (Why is no real title available?)
• scientific article; zbMATH DE number 1849109 (Why is no real title available?)
• scientific article; zbMATH DE number 1941139 (Why is no real title available?)

Describes a project that uses

Uses Software

• SPARSKIT

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