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A systematic and comprehensive treatment of power modeling and optimization at logic level is lacking today. It is the intention of the present book to occupy this niche area. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. The book contains detailed descriptions of technology-independent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints. The book is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis. Emphasis is given to top-down structured design flow for ASICs. Examples and benchmark results are presented to qualitatively and quantitatively assess the effectiveness of various point tools and techniques used in the overall design flow. The book can also be used as a textbook for teaching an advanced course on low power logic synthesis. Instructors can select various combinations of chapters and augment them with some of the many references included at the end of each chapter and material selected from a standard textbook on logic synthesis.