No label defined (Q4398722)

The book handles the design of area-efficient processing units that can execute one or more functions in one or nore clock cycles at a high clock frequency. The functions are part of a signal-processing algorithm specifying the behavior of a digital electronic system. The processing units find their application in video signal processors as part of an integrated circuit. A formal model has been set up which is used to formally define the processing unit design problem. Functions to be executed are modelled as signal flow graphs consisting of operations that communicate via signals. Using this model, the processing unit design problem is formulated as a combinatorial optimization problem where the implementation cost of the processing unit is minimized. The thesis is organized as follows. First a formal model is described that the author uses to describe the processing unit design problem. The next chapter discusses the complexity of the problem. Then solution methods are discussed.