Phased logic: supporting the synchronous design paradigm with delay-insensitive circuitry (Q4420848)
From MaRDI portal
!
This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use the normal view instead:
scientific article; zbMATH DE number 1966787
| Language | Label | Description | Also known as |
|---|---|---|---|
| default for all languages | No label defined |
||
| English | Phased logic: supporting the synchronous design paradigm with delay-insensitive circuitry |
scientific article; zbMATH DE number 1966787 |
Statements
Phased logic: supporting the synchronous design paradigm with delay-insensitive circuitry (English)
0 references
1996
0 references
asynchronous circuitry
0 references
Level-Encoded two-phase Dual-Rail
0 references
0.6718237400054932
0 references
0.6621384620666504
0 references
