FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder (Q4590345)
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scientific article; zbMATH DE number 6809896
| Language | Label | Description | Also known as |
|---|---|---|---|
| default for all languages | No label defined |
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| English | FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder |
scientific article; zbMATH DE number 6809896 |
Statements
FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder (English)
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20 November 2017
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0.87764066
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0.86327344
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0.8601303
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0.8474064
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