FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

DOI10.1109/TCSI.2004.838266MaRDI QIDQ4590345zbMATH OpenFDO

Authors Man Guo, M. Omair Ahmad, M. N. S. Swamy, Chun-Yan Wang

Publication date 20 November 2017

Published in IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Mathematics Subject Classification ID

Decoding (94B35)

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Cited in

(2)

• VLSI architecture and implementation for FS1016 CELP decoder with reduced power and memory requirements
• An Approach for Adaptively Approximating the Viterbi Algorithm to Reduce Power Consumption While Decoding Convolutional Codes

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