FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

DOI10.1109/TCSI.2004.838266zbMATH Open1374.94865MaRDI QIDQ4590345FDOQ4590345

Authors: Man Guo, M. Omair Ahmad, M. N. S. Swamy, Chun-Yan Wang 

Publication date: 20 November 2017

Published in: IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Recommendations

• Error-Resilient Low-Power Viterbi Decoder Architectures
• Low-Latency Low-Complexity Architectures for Viterbi Decoders
• An efficient in-place VLSI architecture for Viterbi algorithm
• Systolic array processing of the Viterbi algorithm
• VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture

Mathematics Subject Classification ID

Decoding (94B35)

Cited In (2)

• VLSI architecture and implementation for FS1016 CELP decoder with reduced power and memory requirements
• An Approach for Adaptively Approximating the Viterbi Algorithm to Reduce Power Consumption While Decoding Convolutional Codes

This page was built for publication: FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4590345)