Low-Latency Low-Complexity Architectures for Viterbi Decoders

DOI10.1109/TCSI.2008.2012217MaRDI QIDQ5010822zbMATH OpenFDO

Authors Renfei Liu, Keshab K. Parhi

Publication date 26 August 2021

Published in IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TCSI.2008.2012217

Mathematics Subject Classification ID

Decoding (94B35)

Cited in

(2)

• scientific article; zbMATH DE number 3494262 (Why is no real title available?)
• FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

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