Systolic array processing of the Viterbi algorithm

DOI10.1109/18.42179MaRDI QIDQ3824232zbMATH OpenOpenAlexFDO

Authors Chi-Yung Chang, Kung Yao

Publication date 1989

Published in IEEE Transactions on Information Theory (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/18.42179

zbMATH Keywords

Viterbi algorithmconvolutional codessystolic arraysstrongly connected trellis decoding

Mathematics Subject Classification ID

Convolutional codes (94B10) Decoding (94B35)

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Cited in

(7)

• scientific article; zbMATH DE number 1504675 (Why is no real title available?)
• Interleaved convolutional code and its Viterbi decoder architecture
• A parallel Viterbi decoder for block cyclic and convolution codes
• Metric based Viterbi decoder node synchronization
• scientific article; zbMATH DE number 139810 (Why is no real title available?)
• An efficient in-place VLSI architecture for Viterbi algorithm
• FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

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