Systolic array processing of the Viterbi algorithm

DOI10.1109/18.42179zbMATH Open0671.94016OpenAlexW1965138518MaRDI QIDQ3824232FDOQ3824232

Authors: Chi-Yung Chang, Kung Yao 

Publication date: 1989

Published in: IEEE Transactions on Information Theory (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/18.42179

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zbMATH Keywords

Viterbi algorithmconvolutional codessystolic arraysstrongly connected trellis decoding

Mathematics Subject Classification ID

Convolutional codes (94B10) Decoding (94B35)

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• An efficient in-place VLSI architecture for Viterbi algorithm
• Title not available (Why is that?)
• FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder
• Interleaved convolutional code and its Viterbi decoder architecture
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• A parallel Viterbi decoder for block cyclic and convolution codes
• Metric based Viterbi decoder node synchronization

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