Analysis of convolutional encoders and synthesis of rate-2/n Viterbi decoders

DOI10.1109/18.508860MaRDI QIDQ4885737zbMATH OpenOpenAlexFDO

Authors S. Summerfield

Publication date 4 February 1997

Published in IEEE Transactions on Information Theory (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/18.508860

zbMATH Keywords

VLSI designconvolutional encodersViterbi decodersmodular VLSI layout

Mathematics Subject Classification ID

Convolutional codes (94B10) Decoding (94B35) Modulation and demodulation in information and communication theory (94A14)

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Cited in

(8)

• Viterbi decoding of the \((63,57)\) Hamming code -- implementation and performance results
• Interleaved convolutional code and its Viterbi decoder architecture
• Realization of 2D convolutional codes of rate \(\frac{1}{n}\) by separable Roesser models
• Some VLSI decompositions of the de Bruijn graph
• On locally invertible rate-1/n convolutional encoders
• Systolic array processing of the Viterbi algorithm
• State diagram connectivity and its effects on the decoding of shift-register-based codes
• An efficient in-place VLSI architecture for Viterbi algorithm

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