Architectural optimization for a 1. 82 Gbits/sec VLSI implementation of the AES Rijndael algorithm (Q4797387)
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scientific article; zbMATH DE number 1882019
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| English | Architectural optimization for a 1. 82 Gbits/sec VLSI implementation of the AES Rijndael algorithm |
scientific article; zbMATH DE number 1882019 |
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3 April 2003
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0.8423296809196472
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0.8399987816810608
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0.8279543519020081
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0.8271763324737549
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0.82005375623703
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Architectural optimization for a 1. 82 Gbits/sec VLSI implementation of the AES Rijndael algorithm (English)
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