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Whilst most textbooks on hardware description languages are devoted to the explanation of the language itself and their application in the field of specifying (synthesizable) designs, up to 70\ million gate ASIC projects is spend in design verification. This textbook is the first one devoted exclusively to the verification process and the systematic use of HDLs and simulation within this verification process. All problems and examples are illustrated by Verilog and VHDL, the two most popular languages in practical use. The first three chapters describe the verification process and several practical aspects of this process from project management to tools that support the verification process. Chapter 4 focusses on behavioral modelling. This is a very important aspect in verification. Verification requires a model of the environment of a design. Most people working in the field of ASIC design are very well educated in designing synthesizable RTL models. Often they are not aware of the possibilities of HDLs in behavioral modelling. Therefore, if they are asked to model the environment behavior they are likely to do this by an expensive, time consuming and error prone RTL implemention of the environment. Chapter 4 illustrates how to model the environment behavior and how to encapsulate and abstract from its complexity. Chapter 5 is devoted to the complex task of stimulus generation and response checking during verification. It presents many useful techniques of behavioral modeling to interact with the design under verification, to predict the expected output and to check the simulation results. For large designs, the verification code can make up to 80\ project. Therefore, it is important to structure this code very well and to support reuse in later projects. In chapter 6 the author discusses how to structure the verification code into packages, utilities, bus functional models, test harness and test cases. The problem of managing and accelerating simulations during the verification and the design process is adressed in chapter 7. I think, that this book is not only a useful but a mandatory addendum to any textbook on VHDL or Verilog, because they are all too much build around the implementation problem. People who have first design experiences with either Verilog or VHDL and plan their first larger design project will find many valuable advices, ideas and concepts when reading this book.