Dynamically reconfigurable dataflow architecture for high-performance digital signal processing on multi-FPGA platforms. (Q5504133)
From MaRDI portal
!
This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use the normal view instead:
scientific article; zbMATH DE number 5495852
| Language | Label | Description | Also known as |
|---|---|---|---|
| default for all languages | No label defined |
||
| English | Dynamically reconfigurable dataflow architecture for high-performance digital signal processing on multi-FPGA platforms. |
scientific article; zbMATH DE number 5495852 |
Statements
21 January 2009
0 references
computational DSP performance
0 references
data flow architecture
0 references
0.7578542232513428
0 references
0.7340384125709534
0 references
