Dynamically reconfigurable dataflow architecture for high-performance digital signal processing on multi-FPGA platforms.

MaRDI QIDQ5504133zbMATH OpenFDO

Authors Sven-Ole Voigt

Publication date 21 January 2009

Full work available at URL http://www.shaker.de/de/content/catalogue/index.asp?lang=de&ID=8&ISBN=978-3-8322-7805-2

zbMATH Keywords

computational DSP performancedata flow architecture

Mathematics Subject Classification ID

Introductory exposition (textbooks, tutorial papers, etc.) pertaining to computer science (68-01) Computer system organization (68M99)

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• A FPGA-based library for on-line signal processing

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