A bit-level systolic array for digital contour smoothing (Q583841)

A family of linear operators (defined by circulant Toeplitz matrices) for digital contour smoothing in the sense of least-squares is described. In order to ensure a real time computation a two-way linear systolic array of inner product step processors is proposed. The structure of this array allows to implement each operator of the family. For a particular operator, by taking advantage of an appropriate decomposition of the circulant Toeplitz matrix, a systolic design for the basic inner product step processor is presented so that a bit-level implementation of this operator is obtained and the multiplication is performed by shifting operations. The nice features of the proposed systolic algorithm make it quite suitable for VLSI implementation.