Modeling out-of-order processors for WCET analysis (Q853636)
From MaRDI portal
| This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use this page instead for the normal view: Modeling out-of-order processors for WCET analysis |
scientific article; zbMATH DE number 5073640
| Language | Label | Description | Also known as |
|---|---|---|---|
| default for all languages | No label defined |
||
| English | Modeling out-of-order processors for WCET analysis |
scientific article; zbMATH DE number 5073640 |
Statements
Modeling out-of-order processors for WCET analysis (English)
0 references
17 November 2006
0 references
Worst-case execution time analysis
0 references
Out-of-order superscalar processor
0 references
Instruction cache
0 references
Branch prediction
0 references
0.8363335728645325
0 references
0.8213893175125122
0 references
0.7679774761199951
0 references