Modeling out-of-order processors for WCET analysis

DOI10.1007/s11241-006-9205-5zbMath1103.68410OpenAlexW2064639033MaRDI QIDQ853636

Abhik Roychoudhury, Tulika Mitra, Xian-Feng Li

Publication date: 17 November 2006

Published in: Real-Time Systems (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s11241-006-9205-5

zbMATH Keywords

Branch predictionInstruction cacheOut-of-order superscalar processorWorst-case execution time analysis

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Theory of software (68N99)

Uses Software

• CPLEX
• SimpleScalar

Cites Work

• Modeling control speculation for timing analysis
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