Modeling out-of-order processors for WCET analysis

DOI10.1007/S11241-006-9205-5MaRDI QIDQ853636zbMATH OpenOpenAlexFDO

Authors Abhik Roychoudhury, Tulika Mitra, Xianfeng Li

Publication date 17 November 2006

Published in Real-Time Systems (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s11241-006-9205-5

zbMATH Keywords

Branch predictionInstruction cacheOut-of-order superscalar processorWorst-case execution time analysis

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Theory of software (68N99)

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Cites work

• scientific article; zbMATH DE number 1948403 (Why is no real title available?)
• scientific article; zbMATH DE number 2017361 (Why is no real title available?)
• scientific article; zbMATH DE number 830949 (Why is no real title available?)
• Modeling control speculation for timing analysis

Cited in

(5)

• scientific article; zbMATH DE number 2017361 (Why is no real title available?)
• An exploration of instruction fetch requirement in out-of-order superscalar processors
• scientific article; zbMATH DE number 1948403 (Why is no real title available?)
• A time-predictable VLIW processor and its compiler support
• Modeling control speculation for timing analysis

Describes a project that uses

Uses Software

• SimpleScalar
• CPLEX

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