Modeling out-of-order processors for WCET analysis

DOI10.1007/S11241-006-9205-5zbMATH Open1103.68410OpenAlexW2064639033MaRDI QIDQ853636FDOQ853636

Authors: Abhik Roychoudhury, Tulika Mitra, Xianfeng Li 

Publication date: 17 November 2006

Published in: Real-Time Systems (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s11241-006-9205-5

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zbMATH Keywords

Branch predictionInstruction cacheOut-of-order superscalar processorWorst-case execution time analysis

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Theory of software (68N99)

Cites Work

• Modeling control speculation for timing analysis
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Cited In (5)

• Title not available (Why is that?)
• An exploration of instruction fetch requirement in out-of-order superscalar processors
• Title not available (Why is that?)
• A time-predictable VLIW processor and its compiler support
• Modeling control speculation for timing analysis

Uses Software

• CPLEX
• SimpleScalar

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