SimpleScalar
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Cited in
(45)- Scalability and parallel execution of warp processing: Dynamic hardware/software partitioning
- Chronos
- GNU Fortran
- Performance evaluation of network processor architectures: Combining simulation with analytical estimation.
- Online ensemble learning: An empirical study
- SoftExplorer
- MiBench
- Towards a first vertical prototyping of an extremely fine-grained parallel programming approach
- Evaluation and choice of various branch predictors for low-power embedded processor
- MediaBench
- SPECjvm98
- SPLASH-2
- Tolerating radiation-induced transient faults in modern processors
- DISE
- SESC
- Chronos: A timing analyzer for embedded software
- Using FORAY models to enable MPSoC memory optimizations
- aiT
- SMA: A self-monitored adaptive cache warm-up scheme for microprocessor simulation
- Image Processing Toolbox
- ALPBench
- Wattch
- CHStone
- scientific article; zbMATH DE number 1690165 (Why is no real title available?)
- scientific article; zbMATH DE number 1690167 (Why is no real title available?)
- A framework for memory contention analysis in multi-core platforms
- M-Sim
- On the modular integration of abstract semantics for WCET analysis
- McPAT
- PCL
- Synchronization coherence: a transparent hardware mechanism for cache coherence and fine-grained synchronization
- eCACTI
- A case for interval hardware on superscalar processors
- Evaluating the impact of accurate branch prediction on interval software
- scientific article; zbMATH DE number 2087558 (Why is no real title available?)
- scientific article; zbMATH DE number 1875367 (Why is no real title available?)
- Languages and Compilers for Parallel Computing
- Overview on a formal model of architecture/circuit trade-offs for the implementation of fast processors
- Dynamic partitioning of shared cache memory
- Modeling out-of-order processors for WCET analysis
- Avoiding conversion and rearrangement overhead in SIMD architectures
- A case for chip multiprocessors based on the data-driven multithreading model
- The impact of speculative execution on SMT processors
- A spatially triggered dissipative resource distribution policy for SMT processors
- Improving adaptability and per-core performance of many-core processors through reconfiguration
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