MiBench

swMATH4421MaRDI QIDQ16597FDOQ16597

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Official website: http://www.eecs.umich.edu/mibench/

Cited In (60)

• COMPCERTSFI
• Energy-aware assignment and scheduling for hybrid main memory in embedded systems
• A novel instruction stream buffer for VLIW architectures
• An exact algorithm for the sequential ordering problem and its application to switching energy minimization in compilers
• Automatic design of application specific instruction set extensions through dataflow graph exploration
• Non-blocking Patricia tries with replace operations
• Code transformations for TLB power reduction
• Improving adaptability and per-core performance of many-core processors through reconfiguration
• Evaluation and choice of various branch predictors for low-power embedded processor
• Hybrid heuristics for optimizing energy consumption in embedded systems
• Using on-chip networks to implement polymorphism in the co-design of object-oriented embedded systems
• Finding optimal hardware/software partitions
• Title not available (Why is that?)
• A profile-based tool for finding pipeline parallelism in sequential programs
• The QC-2 parallel queue processor architecture
• A compiler-hardware approach to software protection for embedded systems
• An algorithm for finding input-output constrained convex sets in an acyclic digraph
• Speculative parallelization of sequential loops on multicores
• Using FORAY models to enable MPSoC memory optimizations
• Algorithms for generating convex sets in acyclic digraphs
• GILK
• Title not available (Why is that?)
• ISDL
• DELI
• PARSEC
• ArchC
• Ibis
• MediaBench
• SUIF
• STAMP
• SPLASH-2
• DISE
• SimpleScalar
• SESC
• CHStone
• SensorSim
• Wattch
• Metropolis
• PATRICIA
• ARMor
• AUSPICE-R
• Sigma*
• Sigma*
• CompCertS
• Rocksalt
• FRIDGE
• HAS-SOP
• Diablo
• Lava
• ADAPT
• QEMU
• eCACTI
• Hardware/software optimization for array {\&} pointer boundary checking against buffer overflow attacks
• Trident
• The ArchC architecture description language and tools
• Modulo path history for the reduction of pipeline overheads in path-based neural branch predictors
• Probabilistic analysis of steady-state temperature and maximum frequency of multicore processors considering workload variation
• Embedded-TM: energy and complexity-effective hardware transactional memory for embedded multicore systems
• AUSPICE-R: automatic safety-property proofs for realistic features in machine code
• Evaluating the Kernighan-Lin Heuristic for Hardware/Software Partitioning

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