MiBench
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Cited in
(62)- A compiler-hardware approach to software protection for embedded systems
- Algorithms for generating convex sets in acyclic digraphs
- GILK
- SoftExplorer
- ISDL
- POLIS
- DELI
- Probabilistic analysis of steady-state temperature and maximum frequency of multicore processors considering workload variation
- Automatic design of application specific instruction set extensions through dataflow graph exploration
- Evaluation and choice of various branch predictors for low-power embedded processor
- ArchC
- Ibis
- Non-blocking Patricia tries with replace operations
- SUIF
- MediaBench
- STAMP
- SPLASH-2
- PARSEC
- An exact algorithm for the sequential ordering problem and its application to switching energy minimization in compilers
- SimpleScalar
- DISE
- SESC
- Using on-chip networks to implement polymorphism in the co-design of object-oriented embedded systems
- Finding optimal hardware/software partitions
- Using FORAY models to enable MPSoC memory optimizations
- The ArchC architecture description language and tools
- Hardware/software optimization for array {\&} pointer boundary checking against buffer overflow attacks
- Energy-aware assignment and scheduling for hybrid main memory in embedded systems
- SensorSim
- Wattch
- CHStone
- Metropolis
- PATRICIA
- Sigma*
- AUSPICE-R
- ARMor
- AUSPICE-R: automatic safety-property proofs for realistic features in machine code
- Sigma*
- CompCertS
- Rocksalt
- FRIDGE
- HAS-SOP
- Diablo
- Lava
- ADAPT
- QEMU
- The QC-2 parallel queue processor architecture
- scientific article; zbMATH DE number 2017359 (Why is no real title available?)
- eCACTI
- An algorithm for finding input-output constrained convex sets in an acyclic digraph
- scientific article; zbMATH DE number 2090859 (Why is no real title available?)
- Hybrid heuristics for optimizing energy consumption in embedded systems
- Evaluating the Kernighan-Lin Heuristic for Hardware/Software Partitioning
- Trident
- COMPCERTSFI
- Embedded-TM: energy and complexity-effective hardware transactional memory for embedded multicore systems
- Speculative parallelization of sequential loops on multicores
- Modulo path history for the reduction of pipeline overheads in path-based neural branch predictors
- A novel instruction stream buffer for VLIW architectures
- Code transformations for TLB power reduction
- Improving adaptability and per-core performance of many-core processors through reconfiguration
- A profile-based tool for finding pipeline parallelism in sequential programs
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