SPLASH-2
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Cited in
(52)- Branch history register cache
- Transparent adaptation of sharing granularity in MultiView-based DSM systems
- Sensitivity of parallel applications to large differences in bandwidth and latency in two-layer interconnects
- Communication characteristics of large-scale scientific applications for contemporary cluster architectures.
- Instruction-throughput regulation in computer processors with data-center applications
- A case for chip multiprocessors based on the data-driven multithreading model
- A hybrid approach for the modelling and simulation of a virtually shared memory parallel computer architecture
- A shared-memory implementation of the hierarchical radiosity method
- Efficient utilization of shared caches in multicore architectures
- Performance regulation of event-driven dynamical systems using infinitesimal perturbation analysis
- Hypermatrix oriented supernode amalgamation
- SPARSEM
- StreamIt
- PERMAS
- KORBX
- MiBench
- PARSEC
- NAS Parallel Benchmarks
- Grace
- MediaBench
- STMBench7
- Lee-TM
- Minebench
- STAMP
- Specomp
- WormBench
- NetLogger
- SimpleScalar
- Fortress
- GDB
- ALPBench
- ParADE
- Wattch
- SoCLib
- AtomCaml
- AVIO
- GraphBIG
- Kendo
- McPAT
- PCL
- tm_db
- TMunit
- A queueing theoretic approach for performance evaluation of low-power multi-core embedded systems
- Data race avoidance and replay scheme for developing and debugging parallel programs on distributed shared memory systems
- Dynamic data prefetching in home-based software DSMs
- Design and implementation of an agent home scheme strategy for prefetch-based DSM systems
- JESSICA2
- Extensible transactional memory testbed
- Analysis of a sparse hypermatrix Cholesky with fixed-sized blocking
- scientific article; zbMATH DE number 1753844 (Why is no real title available?)
- Lightweight transactional memory systems for NoCs based architectures: design, implementation and comparison of two policies
- Limited multiple-writer: An approach to dealing with false sharing in software DSMs
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