Reliable buffered clock tree routing algorithm with process variation tolerance (Q866187)

When IC technology is scaled into the very deep sub-micron regime, the optical proximity effects (OPE) turn into noticeable in optical lithography. Consequently, clock skew becomes more and more susceptible to process variations, such as OPE. In this paper, we propose a new buffered clock tree routing algorithm to prevent the influence of OPE and process variations to clock skew. Based on the concept of BSF (branch sensitivity factor), our algorithm manages to reduce the skew sensitivity of the clock tree in the topology generation. The worst case skew due to the wire width change has been estimated, and proper buffers are inserted to avoid large capacitance load. Experimental results show that our algorithm can produce a more reliable, process-insensitive clock tree, and control clock skews in their permissible range evidently.