Jitter Minimization in Digital PLLs with Mid-Rise TDCs

DOI10.1109/TCSI.2019.2959252MaRDI QIDQ5008363zbMATH OpenOpenAlexFDO

Authors Luca Avallone, Saleh Karman, Carlo Samori, Salvatore Levantino, M. P. Kennedy

Publication date 26 August 2021

Published in IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tcsi.2019.2959252

Mathematics Subject Classification ID

Circuits in qualitative investigation and simulation of models (94C60)

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Cited in

(2)

• Analysis of the PLL Jitter Due to Power/Ground and Substrate Noise
• PREDICTING THE JITTER OF PLL–DLL BASED FREQUENCY SYNTHESIZERS

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