Clock Jitter Compensation in High-Rate ADC Circuits

DOI10.1109/TSP.2012.2208958MaRDI QIDQ4574108zbMATH OpenFDO

Authors Zaid J. Towfic, Shang-Kee Ting, Ali H. Sayed

Publication date 18 July 2018

Published in IEEE Transactions on Signal Processing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TSP.2012.2208958

Mathematics Subject Classification ID

Cited in

(3)

• Modeling of jitter in bang-bang clock and data recovery circuits
• Jitter Minimization in Digital PLLs with Mid-Rise TDCs
• Sinusoidal Clock Sampling for Multigigahertz ADCs

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