Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging

DOI10.1109/TC.2011.192MaRDI QIDQ5274598zbMATH OpenOpenAlexFDO

Authors Ho Fai Ko, Nicola Nicolici

Publication date 12 July 2017

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.2011.192

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Theory of software (68N99)

Recommendations

• On a New Mechanism of Trigger Generation for Post-Silicon Debugging
• A Selective Trigger Scan Architecture for VLSI Testing

Cited in

(1)

• On a New Mechanism of Trigger Generation for Post-Silicon Debugging

This page was built for publication: Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5274598)