A Selective Trigger Scan Architecture for VLSI Testing

DOI10.1109/TC.2007.70806MaRDI QIDQ4589553zbMATH OpenFDO

Authors Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi

Publication date 10 November 2017

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15) Mathematical problems of computer architecture (68M07)

Cited in

(3)

• On a New Mechanism of Trigger Generation for Post-Silicon Debugging
• Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging
• An adaptive heuristic algorithm for VLSI test vectors selection

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