A Selective Trigger Scan Architecture for VLSI Testing

DOI10.1109/TC.2007.70806zbMATH Open1373.68025MaRDI QIDQ4589553FDOQ4589553

Authors: Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi 

Publication date: 10 November 2017

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15) Mathematical problems of computer architecture (68M07)

Cited In (3)

• On a New Mechanism of Trigger Generation for Post-Silicon Debugging
• Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging
• An adaptive heuristic algorithm for VLSI test vectors selection

This page was built for publication: A Selective Trigger Scan Architecture for VLSI Testing

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4589553)