Mapping dynamic programming onto a linear systolic array

DOI10.1007/BF00929926MaRDI QIDQ5753763zbMATH OpenFDO

Authors V. K. Prasanna Kumar, Yu-Chen Tsai

Publication date 1990

Published in Journal of VLSI signal processing systems for signal, image and video technology (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/BF00929926

zbMATH Keywords

efficient implementationfault-tolerant wafer scale integration modellinear array

Mathematics Subject Classification ID

Cellular automata (computational aspects) (68Q80) Computational methods for problems pertaining to operations research and mathematical programming (90-08) Dynamic programming (90C39)

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Cited in

(5)

• The mapping of two-dimensional array processors to one-dimensional processors
• A systolic algorithm for dynamic programming
• Mapping dynamic programming onto modular linear systolic arrays
• Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
• Path planning on the warp computer: using a linear systolic array in dynamic programming^∗

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