Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
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Cited in
(54)- Two-dimensional iterative arrays: Characterizations and applications
- Automatic design and partitioning of systolic/wavefront arrays for VLSI
- Decoupling the dimensions of a system of affine recurrence equations
- A methodology for algorithm regularization and mapping into time-optimal VLSI arrays
- Systolic partitioning algorithms
- Synthesis aspects in the design of efficient processor arrays from affine recurrence equations
- Geometrical tools to map systems of affine recurrence equations on regular arrays
- The design of optimal planar systolic arrays for matrix multiplication
- Method of constructing parallel forms of algorithms based on locally parallel, globally sequential partition
- A unifying lattice-based approach for the partitioning of systolic arrays via LPGS and LSGP
- An experimental evaluation of local search heuristics for graph partitioning
- Design of parallel algorithms for the single resource allocation problem
- Matrix-vector multiplication on a fixed-size linear systolic array
- Designing of processor-time optimal systolic arrays for band matrix-vector multiplication
- Efficient computing methods for parallel processing: An implementation of the Viterbi algorithm
- A parallel algorithm for generating combinations
- A systolic generation of combinations
- A new algorithm for the integer knapsack problem and its parallelization
- Mapping dynamic programming onto modular linear systolic arrays
- Automatic array partitioning based on the Smith normal form
- Folding transformations for processor arrays
- COMBINING BACKGROUND MEMORY MANAGEMENT AND REGULAR ARRAY CO-PARTITIONING, ILLUSTRATED ON A FULL MOTION ESTIMATION KERNEL
- To the role of decomposition strategy in high parallel algorithms
- LOWER TIME AND PROCESSOR BOUNDS FOR EFFICIENT MAPPING OF UNIFORM DEPENDENCE ALGORITHMS INTO SYSTOLIC ARRAYS
- THE MAGIC OF INTERLOCKING PROPERTY: FAST SYSTOLIC DESIGN
- Partitioning of processor arrays: a piecewise regular approach
- Refinement based techniques for mapping nested loop algorithms onto linear systolic arrays
- Synthesizing linear array algorithms from nested FOR loop algorithms
- scientific article; zbMATH DE number 1192974 (Why is no real title available?)
- Fast linear systolic matrix vector multiplication
- Nonlinear transformations of the matrix multiplication algorithm
- Overcoming chip-to-chip delays and clock skews
- EFFICIENT MAPPING REDUCTIONS USING ISO-PLANES ON THE POLYTOPE MODEL
- scientific article; zbMATH DE number 1330074 (Why is no real title available?)
- Algorithm transformations for computational and data broadcast
- From the theory to the tools: parallel dynamic programming
- Double pipelines and fast systolic designs on linear arrays
- Advanced Regular Array Design
- Space-Time Equations for Non-Unimodular Mappings
- Decomposing polynomial interpolation for systolic arrays
- FINDING OPTIMUM WAVEFRONT OF PARALLEL COMPUTATION∗
- A PARALLEL ALGORITHM FOR THE INTEGER KNAPSACK PROBLEM FOR PIPELINE NETWORKS
- A NEW APPROACH TO FINDING OPTIMAL LINEAR SCHEDULES FOR UNIFORM DEPENDENCE ALGORITHMS†
- MODULAR FIXED-SIZE VLSI ARCHITECTURES FOR GENERAL MULTISPLITTING ITERATION
- Algorithm transformations for the data broadcast elimination method
- On mapping algorithms to linear and fault-tolerant systolic arrays
- On high-speed computing with a programmable linear array
- Optimal piecewise linear schedules for LSGP- and LPGS-decomposed array processors via quadratic programming
- Automatic synthesis of parallel algorithms
- Towards systolizing compilation
- Computing transitive closure on systolic arrays of fixed size
- A VLSI systolic architecture for solving DBT-transformed fuzzy clustering problems of arbitrary size
- Some complexity results in parallel matrix-based signal processing
- The projection of systolic programs
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