MODULAR FIXED-SIZE VLSI ARCHITECTURES FOR GENERAL MULTISPLITTING ITERATION

DOI10.1080/10637199508915530MaRDI QIDQ4820129zbMATH OpenOpenAlexFDO

Authors E. Papadopoulou, Y. G. Saridakis

Publication date 6 October 2004

Published in Parallel Algorithms and Applications (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1080/10637199508915530

Mathematics Subject Classification ID

Computer system organization (68M99)

Cites work

• scientific article; zbMATH DE number 51132 (Why is no real title available?)
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• A family of new efficient arrays for matrix multiplication
• Convergence of parallel multisplitting iterative methods for M-matrices
• MODULAR FIXED-SIZE VLSI ARCHITECTURES FOR GENERAL MULTISPLITTING ITERATION
• Multi-Splittings of Matrices and Parallel Solution of Linear Systems
• Parallel Algorithms for Nonlinear Problems
• Parallel algorithms and architectures for multisplitting iterative methods
• Partitioned Matrix Algorithms for VLSI Arithmetic Systems
• Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
• Solution of Partial Differential Equations on Vector and Parallel Computers
• The Design of Optimal Systolic Arrays

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• MODULAR FIXED-SIZE VLSI ARCHITECTURES FOR GENERAL MULTISPLITTING ITERATION

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