Partitioning of processor arrays: a piecewise regular approach
From MaRDI portal
Recommendations
- Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
- scientific article; zbMATH DE number 2079653
- Partitioning processor arrays under resource constraints
- scientific article; zbMATH DE number 4094822
- A unifying lattice-based approach for the partitioning of systolic arrays via LPGS and LSGP
Cited in
(32)- The mapping of two-dimensional array processors to one-dimensional processors
- Implementation of folding transformations on linear VSLI processor arrays
- On the complexity of assembly partitioning
- Method of constructing parallel forms of algorithms based on locally parallel, globally sequential partition
- Partitioning processor arrays under resource constraints
- Generalized multipartitioning of multi-dimensional arrays for parallelizing line-sweep compu\-ta\-tions.
- Partitioning a set of vectors with integer coordinates by means of logical hardware
- Automatic array partitioning based on the Smith normal form
- COMBINING BACKGROUND MEMORY MANAGEMENT AND REGULAR ARRAY CO-PARTITIONING, ILLUSTRATED ON A FULL MOTION ESTIMATION KERNEL
- Optimal folding of data flow graphs based on finite projective geometry using vector space partitioning
- Partitioning program to cadres for computers with dynamically reconfigurable pipeline
- Resource-constrained scheduling of partitioned algorithms on processor arrays
- Systematic serialisation of array-based architectures
- New conception and algorithm of allocation mapping for processor arrays implemented into multi-context FPGA devices
- Mapping Homogeneous Graphs on Linear Arrays
- scientific article; zbMATH DE number 4094822 (Why is no real title available?)
- scientific article; zbMATH DE number 1190794 (Why is no real title available?)
- scientific article; zbMATH DE number 1192974 (Why is no real title available?)
- A Systematically Designed Binary Array Processor
- scientific article; zbMATH DE number 125141 (Why is no real title available?)
- scientific article; zbMATH DE number 125178 (Why is no real title available?)
- scientific article; zbMATH DE number 139974 (Why is no real title available?)
- EFFICIENT MAPPING REDUCTIONS USING ISO-PLANES ON THE POLYTOPE MODEL
- scientific article; zbMATH DE number 1314572 (Why is no real title available?)
- Design of space-optimal regular arrays for algorithms with linear schedules
- scientific article; zbMATH DE number 2040836 (Why is no real title available?)
- scientific article; zbMATH DE number 2079653 (Why is no real title available?)
- Advanced Regular Array Design
- scientific article; zbMATH DE number 882119 (Why is no real title available?)
- Models of two-layer array processors generated by parallel substitution algorithms
- Design of processor arrays for reconfigurable architectures
- A reindexing based approach towards mapping of DAG with affine schedules onto parallel embedded systems
This page was built for publication: Partitioning of processor arrays: a piecewise regular approach
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3136229)