Implementation of folding transformations on linear VSLI processor arrays
From MaRDI portal
Publication:1195159
DOI10.1016/0167-8191(92)90088-OzbMath0792.68001MaRDI QIDQ1195159
Publication date: 7 October 1992
Published in: Parallel Computing (Search for Journal in Brave)
data dependence; systolic array; processor array; algorithm transformation; folding transformation; interlocking translation; partitioned linear transformation; symmetric mapping
Related Items
FOLDING TRANSFORMATIONS ON SYSTOLIC AND VLSI PROCESSOR ARRAYS, FOLDING TECHNIQUES FOR SYSTOLIC ITERATIONS, INTERLOCKING PROPERTIES OF THE LINEAR DATA DEPENDENCE METHOD, Matrix-vector multiplication on a fixed-size linear systolic array, THE MAGIC OF INTERLOCKING PROPERTY: FAST SYSTOLIC DESIGN