A unifying lattice-based approach for the partitioning of systolic arrays via LPGS and LSGP

DOI10.1023/A:1007944932429zbMATH Open0887.68006OpenAlexW2165965906MaRDI QIDQ1376401FDOQ1376401

Karl-Heinz Zimmermann

Publication date: 17 December 1997

Published in: Journal of VLSI signal processing systems for signal, image and video technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1007944932429

zbMATH Keywords

systolic arrayslocally sequential-globally parallelpartitioning schemes

Mathematics Subject Classification ID

Computer system organization (68M99)

Cited In (6)

• Partitioning of processor arrays: a piecewise regular approach
• Systematic serialisation of array-based architectures
• Automatic implementation of affine iterative algorithms: Design flow and communication synthesis
• Optimal piecewise linear schedules for LSGP- and LPGS-decomposed array processors via quadratic programming
• Systolic partitioning algorithms
• On loop transformations of nested loops with affine dependencies

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