Partitioning of processor arrays: a piecewise regular approach
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Publication:3136229
DOI10.1016/0167-9260(93)90013-3zbMATH Open0777.68024OpenAlexW2082711009MaRDI QIDQ3136229FDOQ3136229
Authors: Jürgen Teich, Lothar Thiele
Publication date: 17 October 1993
Published in: Integration (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1016/0167-9260(93)90013-3
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Cited In (28)
- COMBINING BACKGROUND MEMORY MANAGEMENT AND REGULAR ARRAY CO-PARTITIONING, ILLUSTRATED ON A FULL MOTION ESTIMATION KERNEL
- Automatic array partitioning based on the Smith normal form
- EFFICIENT MAPPING REDUCTIONS USING ISO-PLANES ON THE POLYTOPE MODEL
- Partitioning a set of vectors with integer coordinates by means of logical hardware
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- Generalized multipartitioning of multi-dimensional arrays for parallelizing line-sweep compu\-ta\-tions.
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- A Systematically Designed Binary Array Processor
- New conception and algorithm of allocation mapping for processor arrays implemented into multi-context FPGA devices
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- Partitioning program to cadres for computers with dynamically reconfigurable pipeline
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- Resource-constrained scheduling of partitioned algorithms on processor arrays
- Systematic serialisation of array-based architectures
- Advanced Regular Array Design
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- A reindexing based approach towards mapping of DAG with affine schedules onto parallel embedded systems
- Design of processor arrays for reconfigurable architectures
- Title not available (Why is that?)
- The mapping of two-dimensional array processors to one-dimensional processors
- Implementation of folding transformations on linear VSLI processor arrays
- Mapping Homogeneous Graphs on Linear Arrays
- Design of space-optimal regular arrays for algorithms with linear schedules
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- Optimal folding of data flow graphs based on finite projective geometry using vector space partitioning
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