Partitioning of processor arrays: a piecewise regular approach

DOI10.1016/0167-9260(93)90013-3zbMATH Open0777.68024OpenAlexW2082711009MaRDI QIDQ3136229FDOQ3136229

Lothar Thiele, Jürgen Teich

Publication date: 17 October 1993

Published in: Integration (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0167-9260(93)90013-3

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zbMATH Keywords

clusteringpartitioningalgorithm transformationVLSI processor arraysfixed size arraysmapping of algorithms

Mathematics Subject Classification ID

Distributed algorithms (68W15) Mathematical problems of computer architecture (68M07)

Cited In (23)

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• Automatic array partitioning based on the Smith normal form
• EFFICIENT MAPPING REDUCTIONS USING ISO-PLANES ON THE POLYTOPE MODEL
• Partitioning a set of vectors with integer coordinates by means of logical hardware
• On the complexity of assembly partitioning
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• Generalized multipartitioning of multi-dimensional arrays for parallelizing line-sweep compu\-ta\-tions.
• Title not available (Why is that?)
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• A Systematically Designed Binary Array Processor
• Title not available (Why is that?)
• Title not available (Why is that?)
• Resource-constrained scheduling of partitioned algorithms on processor arrays
• Systematic serialisation of array-based architectures
• Advanced Regular Array Design
• Title not available (Why is that?)
• A reindexing based approach towards mapping of DAG with affine schedules onto parallel embedded systems
• Design of processor arrays for reconfigurable architectures
• The mapping of two-dimensional array processors to one-dimensional processors
• Implementation of folding transformations on linear VSLI processor arrays
• Mapping Homogeneous Graphs on Linear Arrays
• Design of space-optimal regular arrays for algorithms with linear schedules
• Title not available (Why is that?)

Uses Software

• REDUCE

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