Partitioning of processor arrays: a piecewise regular approach

DOI10.1016/0167-9260(93)90013-3zbMath0777.68024OpenAlexW2082711009MaRDI QIDQ3136229

Lothar Thiele, Jürgen Teich

Publication date: 17 October 1993

Published in: Integration (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0167-9260(93)90013-3

zbMATH Keywords

partitioningclusteringalgorithm transformationVLSI processor arraysfixed size arraysmapping of algorithms

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Distributed algorithms (68W15)

Related Items (4)

Advanced Regular Array Design ⋮ A reindexing based approach towards mapping of DAG with affine schedules onto parallel embedded systems ⋮ COMBINING BACKGROUND MEMORY MANAGEMENT AND REGULAR ARRAY CO-PARTITIONING, ILLUSTRATED ON A FULL MOTION ESTIMATION KERNEL ⋮ EFFICIENT MAPPING REDUCTIONS USING ISO-PLANES ON THE POLYTOPE MODEL

Uses Software

• REDUCE

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