New conception and algorithm of allocation mapping for processor arrays implemented into multi-context FPGA devices

zbMATH Open1197.68087MaRDI QIDQ3565737FDOQ3565737

Authors: Piotr Ratuszniak, Oleg V. Maslennikov 

Publication date: 7 June 2010

Recommendations

• Design of processor arrays for reconfigurable architectures
• Partitioning of processor arrays: a piecewise regular approach
• A methodology for algorithm regularization and mapping into time-optimal VLSI arrays
• Configuring of algorithms in mapping into hardware
• Automatic synthesis of FPGA processor arrays from loop algorithms

zbMATH Keywords

allocation mappingCholesky's algorithm for banded matricesmulti-context programmable devices

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cited In (2)

• Architecture-Aware Technique for Mapping Area-Time Efficient Custom Instructions onto FPGAs
• Configuring of algorithms in mapping into hardware

This page was built for publication: New conception and algorithm of allocation mapping for processor arrays implemented into multi-context FPGA devices

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3565737)