On high-speed computing with a programmable linear array
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Recommendations
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- scientific article; zbMATH DE number 1751891
Cites work
- Mapping Homogeneous Graphs on Linear Arrays
- Modular Matrix Multiplication on a Linear Array
- Partitioned Matrix Algorithms for VLSI Arithmetic Systems
- Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
- The Design of Optimal Systolic Arrays
- The parallel execution of DO loops
- Time and Parallel Processor Bounds for Fortran-Like Loops
Cited in
(7)- A Systematically Designed Binary Array Processor
- Speeding up the systolic design in bidirectional linear arrays
- On the virtual array concept for higher order array processing
- A programmable systolic device for image processing based on mathematical morphology
- Double pipelines and fast systolic designs on linear arrays
- High-Speed Parallel Architectures for Linear Feedback Shift Registers
- Array control for high-performance SIMD systems
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