High-Speed Parallel Architectures for Linear Feedback Shift Registers

DOI10.1109/TSP.2011.2159495zbMATH Open1392.94902OpenAlexW2163568316MaRDI QIDQ4573199FDOQ4573199

Authors: Manohar Ayinala, Keshab K. Parhi 

Publication date: 18 July 2018

Published in: IEEE Transactions on Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tsp.2011.2159495

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Mathematics Subject Classification ID

Communication theory (94A05) Shift register sequences and sequences over finite alphabets in information and communication theory (94A55) Transformations (93B17)

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