On reconfigurability of VLSI linear arrays
DOI10.1007/3-540-57155-8_279zbMATH Open1504.68020OpenAlexW1565362788MaRDI QIDQ5060146FDOQ5060146
Authors: Roberto De Prisco, Angelo Monti 
Publication date: 18 January 2023
Published in: Lecture Notes in Computer Science (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/3-540-57155-8_279
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Analysis of algorithms (68W40) Computational difficulty of problems (lower bounds, completeness, difficulty of approximation, etc.) (68Q17) Reliability, testing and fault tolerance of networks and computer systems (68M15)
Cites Work
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- On the complexity of testing for catastrophic faults
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- Fault tolerant algorithms for a linear array with a reconfigurable pipelined bus system*
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- Linear placement algorithms and applications to VLSI design
- Polymorphic arrays: A novel VLSI layout for systolic computers
- Testing and reconfiguration of VLSI linear arrays
- Counting the number of fault patterns in redundant VLSI arrays
- Catastrophic faults in reconfigurable systolic linear arrays
- Reconfiguration for Repair in a Class of Universal Logic Modules
- The total system reliabilities for fault-tolerant self-reconfigurable array systems
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- Distributed Computing - IWDC 2004
- An Array Layout Methodology for VLSI Circuits
- Reconfiguring Arrays with Faults Part I: Worst-Case Faults
- Title not available (Why is that?)
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