On testing for catastrophic faults in reconfigurable arrays with arbitrary link redundancy

DOI10.1016/0167-9260(96)00005-3MaRDI QIDQ4332022zbMATH OpenOpenAlexFDO

Authors A. Nayak, L. Pagli, N. Santoro

Publication date 27 February 1997

Published in Integration (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0167-9260(96)00005-3

zbMATH Keywords

Fault toleranceTestingSystolic arraysCatastrophic fault patterns

Mathematics Subject Classification ID

Computer system organization (68M99)

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(11)

• On enumeration of catastrophic fault patterns
• On reconfigurability of VLSI linear arrays
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• An improved testing scheme for catastrophic fault patterns
• Enumerating catastrophic fault patterns in VLSI arrays with both uni- and bidirectional links
• Counting the number of fault patterns in redundant VLSI arrays
• Catastrophic faults in reconfigurable systolic linear arrays
• Formal Probabilistic Analysis of Stuck-at Faults in Reconfigurable Memory Arrays
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