On testing for catastrophic faults in reconfigurable arrays with arbitrary link redundancy
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Publication:4332022
DOI10.1016/0167-9260(96)00005-3zbMATH Open0875.68157OpenAlexW2023701305MaRDI QIDQ4332022FDOQ4332022
Authors: A. Nayak, L. Pagli, N. Santoro 
Publication date: 27 February 1997
Published in: Integration (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1016/0167-9260(96)00005-3
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Cited In (11)
- On enumeration of catastrophic fault patterns
- On reconfigurability of VLSI linear arrays
- On the complexity of testing for catastrophic faults
- Characterization of catastrophic faults in two-dimensional reconfigurable systolic arrays with unidirectional links
- An improved testing scheme for catastrophic fault patterns
- Enumerating catastrophic fault patterns in VLSI arrays with both uni- and bidirectional links
- Counting the number of fault patterns in redundant VLSI arrays
- Catastrophic faults in reconfigurable systolic linear arrays
- Formal Probabilistic Analysis of Stuck-at Faults in Reconfigurable Memory Arrays
- Title not available (Why is that?)
- Distributed Computing - IWDC 2004
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