An improved testing scheme for catastrophic fault patterns

DOI10.1016/S0020-0190(00)00012-0zbMATH Open1338.68033OpenAlexW1972637229MaRDI QIDQ294739FDOQ294739

Authors: A. Nayak, J. Ren, N. Santoro 

Publication date: 16 June 2016

Published in: Information Processing Letters (Search for Journal in Brave)

Full work available at URL: http://www.sciencedirect.com/science/article/pii/S0020019000000120?np=y

zbMATH Keywords

algorithmscatastrophic faultsredundant arraystesting schemes

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15)

Cites Work

• Testing and reconfiguration of VLSI linear arrays
• On graphs preserving rectilinear shortest paths in the presence of obstacles
• Counting the number of fault patterns in redundant VLSI arrays
• A note on isomorphic chordal rings
• Catastrophic faults in reconfigurable systolic linear arrays
• Title not available (Why is that?)
• Efficient construction of catastrophic patterns for VLSI reconfigurable arrays
• On testing for catastrophic faults in reconfigurable arrays with arbitrary link redundancy

Cited In (3)

• Irreversible conversion of graphs
• Reversible iterative graph processes
• Triggering cascades on strongly connected directed graphs

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