Fault detection and design complexity in C-testable VLSI arrays

DOI10.1109/12.61070zbMATH Open1395.68056OpenAlexW2038234509MaRDI QIDQ5375459FDOQ5375459

Authors:

Publication date: 14 September 2018

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/12.61070

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15)

Cited In (6)

• On testing for catastrophic faults in reconfigurable arrays with arbitrary link redundancy
• Enumerating catastrophic fault patterns in VLSI arrays with both uni- and bidirectional links
• Testing and Diagnosing Comparison Faults of TCAMs with Asymmetric Cells
• Title not available (Why is that?)
• Design of exclusive or sum-of-products (ESP) logic arrays with universal tests for detecting stuck-at and bridging faults
• Testable design of two-dimensional cellular logic arrays for detecting struck-at and bridging faults

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